As a result of the simultaneous development of the technology and the requirements of the market, improved performances of such electronic systems have demands for an increasingly limited time-to-market.
Furthermore, designers are generally required to design such electronic systems while providing both design flexibilities and better efficiencies in terms of performance, power consumption, and silicon surface area used. This is also denoted by those skilled in the art under the acronym PPA (Performance Power Area), and this is even more the case for onboard systems.
However, the current design for such an electronic system is limited to inefficient integrations between programmable processors and hardware accelerators specific to each application since they are generally loosely coupled via a high-speed communications system. The high-speed communications system may be, for example, a gigabit Ethernet network, and the processors and the hardware accelerators use different communications protocols.
Indeed, generally speaking, the accelerators execute massive parallel stream processing operations, whereas the processors carry out sequential processing operations of the load/store type.
Currently, the level of complexity for programming such an electronic system with conventional tools is often very high. The level of complexity is even more so if parallel processing and a global optimization on the management of the resources, such as the memory and the programmable processors, are taken into account.
In addition, it is difficult to partition such an electronic system into two parts, one hardware part and one software part, since in order to do this these two parts need to be significantly modified. A procedure for exploring or for verifying such an architecture is also time consuming.